1. Field of the Invention
The present invention relates to an oscillator. More particularly, the invention relates to an oscillator capable of reducing variations in the period of a clock signal caused by voltage or temperature variations.
This application claims the benefit of Korean Patent Application No. 10-2006-0040514 filed on May 4, 2006, the subject matter of which is hereby incorporated by reference.
2. Description of the Related Art
Figure (FIG.) 1 is a circuit diagram of a conventional oscillator 10.
Referring to FIG. 1, conventional oscillator 10 includes a reference current generator 11, an RS slope generator 12, and a clock signal generator 13. A reference voltage Vref is derived from a reference current Iref generated by reference current generator 11. Reference voltage Vref is applied to RS slope generator 12.
RS slope generator 12 includes a first inverter INV1 inverting a clock signal CLK in a feedback loop and a second inverter INV2 inverting the logical inverse of the clock signal, hereafter “inverse clock signal”, CLKB. A first capacitor C1 and a second capacitor C2 are charged or discharged according to the respective outputs of the first and second inverters INV1 and INV2.
Since the first and second capacitors C1 and C2 are charged or discharged in response to the clock signal CLK and the inverse clock signal CKLB, a first voltage VC1 across the first capacitor C1 and a second voltage VC2 across the second capacitor C2 are respectively output to generate an output waveform of constant period.
A first amplifier AMP1 of RS slope generator 12 compares the first voltage VC1 with the reference voltage Vref and outputs a first comparison result. A second amplifier AMP2 of RS slope generator 12 compares the second voltage VC2 with the reference voltage Vref and outputs a second comparison result. That is, if either one of the first or second voltages, VC1 or VC2, is higher than the reference voltage Vref, the first or second amplifier AMP1 or AMP2 will output a logically “high” signal. If either of the first or second voltages, VC1 or VC2, is lower than the reference voltage Vref, the first or second amplifier, AMP1 or AMP2, will output a logically “low” signal.
Here, the respective first and second amplifier outputs, XL1 and XL2, have the same period. However, due to a signal delay difference caused by different charging/discharging speeds for the first and second capacitors, C1 and C2, the actual waveform timing of the logic levels communicated at the first and second amplifier outputs XL1 and XL2 are different.
Therefore, clock signal generator 13 includes latches receiving the first and second amplifier outputs XL1 and XL2. An output clock signal CLK and an inverse clock signal CLKB, both having a constant period are then provided by clock signal generator 13. As noted above, these signals are fed back to the first and second inverters INV1 and INV2 of RS slope generator 12, respectively.
However, in order to maintain a constant period for clock signal CLK, the first and second amplifier outputs XL1 and XL2 responsive to comparisons between the first and second voltages VC1 and VC1 and the reference voltage Vref must be maintained at a constant period. This requires that the reference voltage Vref be maintained at a constant amplitude.
However, experience has shown that within the typical operation of conventional oscillator 10, the reference current Iref from which the reference voltage Vref is derived is not maintained at a constant level. Indeed, the reference voltage Vref is known to vary in accordance with variation in the supply voltage (VDD) and/or the operating temperature of the oscillator. Accordingly, conventional oscillator 10 routinely generates a clock signal having an irregular period. Such inconstancy in the period of the clock signal may cause erroneous operation of other circuits whose operation is controlled in relation to the clock signal.
As the operating speed of contemporary semiconductor devices increases, variations in the period of a controlling clock signal become less and less tolerable as they are increasingly likely to cause erroneous operations in associated circuitry.